Oscillators are required within many different technology areas, especially within the expanding communication industry. In communication applications, oscillators are commonly used to generate carrier signals at specific frequencies on which information signals are subsequently modulated. For instance, a Voltage Controlled Oscillator (VCO) within a Personal Communication System (PCS) would typically be tuned around 1900 MHz.
FIG. 1 is a block diagram illustrating a typical Phase Locked Loop-Frequency Synthesizer (PLL-FS) that is a standard implementation for a VCO within a communication apparatus. In the case shown in FIG. 1, the PLL-FS includes a crystal reference oscillator 20, in this case operating at 8 MHz, coupled in series with a first frequency divider 22, a phase detector 24, a loop filter 26, a VCO in the form of a Voltage Controlled-Coaxial Resonator Oscillator (VC-CRO) 28, a coupler 30 that generates a sample of the signal output from the VC-CRO 28, and an amplifier 32 that outputs a signal S.sub.OUT (t). Further, the PLL-FS includes a phase feedback path comprising a second frequency divider 36 coupled between the coupler 30 and the phase detector 24.
Within the block diagram of FIG. 1, the crystal reference oscillator 20 outputs a crystal reference signal at 8 MHz that is subsequently frequency divided down to 160 KHz by the first frequency divider 22. The phase detector 24 receives the divided crystal reference signal and compares its phase with a feedback signal, the generation of the feedback signal being described herein below. The output of the phase detector 24 is a baseband signal, the amplitude of which is proportional to the phase difference between the two signals input to the phase detector 24, along with comparison frequency spurs at integer multiples of 160 KHz. The loop filter 26 (that could be either passive or active) receives the output from the phase detector 24 and removes the spurs within the signal by rejecting the components at multiples (n.times.160 KHz) of the comparison frequency (160 KHz), leaving only the baseband signal. This filtered result is fed as a control voltage into a tuning port 34 of the VC-CRO 28, the frequency of which is controlled with a varactor diode arrangement (not shown). The VC-CRO 28 in this case comprises a Colpitts oscillator stabilized with a ceramic coaxial resonator that creates a signal at an oscillation frequency based upon the frequency of resonance of the particular resonator used and the control voltage applied at the tuning port 34. The oscillation frequency is normally slightly less than that of the frequency of resonance (typically between 200 MHz and 5 GHz). The high frequency signal output from the VC-CRO 28 is sampled by the coupler 30 and frequency divided by the second frequency divider 36 to generate the feedback signal input to the phase detector 24. One should understand that the amount the frequency of the feedback signal is divided within the second frequency divider 36 determines the control voltage output from the phase detector 26. This voltage level subsequently determines the oscillation frequency at which the VC-CRO 28 is tuned, with changes in the division factor allowing for step changes in the oscillation frequency. As depicted in FIG. 1, the output from the VC-CRO 28 is received at the amplifier 32 which amplifies the signal and outputs the amplified result as the signal S.sub.OUT (t). Overall, the PLL synthesizer architecture enables digital control over the VC-CRO frequency, and also locks the VC-CRO to the reference crystal oscillator which ensures the frequency stability of the source over all system conditions such as temperature, ageing, and mechanical stress.
There are a number of advantages of using a ceramic coaxial resonator to stabilize a VC-CRO within a PLL-FS. These advantages relate to the physical design of a ceramic coaxial resonator. Typically, a ceramic coaxial resonator comprises a ceramic dielectric material formed as a rectangular prism with a coaxial hole running lengthwise through the prism and a electrical connector connected to one end. The outer and inner surfaces of the prism, with the exception of the end connected to the electrical connector and possibly the opposite end, are coated in a metal such as copper or silver. A device formed in this manner essentially forms a resonant RF circuit, including capacitance, inductance, and resistance, that oscillates when in the Transverse Electromagnetic (TEM) mode (as is the case when stabilizing a Colpitts oscillator). The advantages gained with this design include a high Q value (typically approx. 800) and therefore low noise oscillations associated with the resonator as well as temperature stability and resistance to microphonics that characterize a ceramic coaxial resonator. These advantages result in a further important advantage, that being a low cost; currently approximately 65 cents per resonator.
Unfortunately, there is a significant problem with the use of ceramic coaxial resonators as currently designed. The frequency of resonance for a ceramic coaxial resonator has a maximum frequency that can be output due to physical limitations. The frequency of resonance for a ceramic coaxial resonator is based upon the physical size and shape of the particular resonator. Generally, the smaller the size of the resonator, the higher is the frequency of resonance and vice versa. The problem is that ceramic coaxial resonators have a minimum size at which they can be manufactured that limits the frequency of resonance equal to or below a maximum value. This is a physical limit that, as currently designed, limits the output of a typical Coaxial Resonator Oscillator (CRO) using a ceramic coaxial resonator to approximately 5 GHz, whether the CRO is voltage controlled or not.
Up until recently, this 5 GHz limit has not significantly affected the use of ceramic coaxial resonators within VC-CROs or CROs since the frequency of operation of previous communication equipment was typically below this level. For example, PCS equipment operate at approximately 1900 MHz. Currently there are a number of different communication standards that require VCOs with oscillation frequencies higher than 5 GHz. For instance, OC-192 fiber optic signals are transmitted at approximately 10 GHz and the newly developed Local Multi-point Distribution System (LMDS), slated to be used for the Internet over wireless, is set to operate between 28 to 30 GHz. It can be assumed that further developments and standards will be designed that require yet higher oscillation frequencies.
One well-known technique to increase the oscillation frequency of signals within a system using a standard VCO as depicted in FIG. 1 is to use a subharmonically pumped mixer that doubles the oscillation frequency at a stage after the VCO. Unfortunately, even with the use of a subharmonically pumped mixer, a system using the standard VCO that operates with a ceramic coaxial resonator is still limited to a maximum oscillation frequency of 10 GHz which is insufficient for LMDS applications. Hence, techniques are required to increase the oscillation frequency within the actual VCOs.
One technique that has been tried to increase the oscillation frequency output from a PLL-FS as depicted in FIG. 1 beyond the 5 GHz limit is to add a frequency multiplication stage after the amplifier 32. An example of such a multiplication stage is illustrated within FIG. 2. As can be seen, a frequency multiplier 38 is coupled to the output of the amplifier 32 and further coupled in series with a first filter 40, an amplifier 42, and a second filter 44. In this design, the multiplier 38 increases the oscillation frequency of the signal by three times that of the frequency output from the amplifier 32. Hence, if the original frequency of the VCO was 5 GHz, this would allow the resulting system frequency (after using a subharmonically pumped mixer) to be 30 GHz. The filters 40,44 and amplifier 42 are used to reduce the noise spurs and other undesirable characteristics added to the signal as a result of the multiplier 38. One problem with this implementation is the inability of the filters 40,44 and amplifier 42 to completely remove the spurs and undesired mixing products output from the multiplier 38, hence passing on these non-ideal characteristics to further components within the system that use the oscillating signal. Another problem is the typically low efficiency of multipliers, such as multiplier 38, that can lead to high current consumption within the circuit by the multiplier 38. Yet further, the added components 38,40,42,44 also add to the component count and cost for the overall PLL-FS.
Another technique that is used to increase the oscillation frequency being output from a VCO is to replace the standard VC-CRO 28 with an oscillator stabilized with an alternative resonator device to the ceramic coaxial resonator. In one implementation, this alternate oscillator is a Dielectric Resonator Oscillator (DRO) which can allow for frequencies higher than 20 GHz to be output. A DRO typically continues to use a Colpitts oscillator while using a dielectric resonator in place of the ceramic coaxial resonator. Dielectric resonators consist of a puck of dielectric material encased within a cavity. The physical dimensions of the puck set the frequency range for a DRO while the placement of the puck within the cavity is critical to the tuning of the center frequency. One of the key disadvantages of the DRO implementation is the cost of tuning the center frequency. Since the puck of a DRO is sensitive with respect to its location within the cavity, the DRO as a whole is susceptible to microphonics, that being mechanical vibration of the resonator housing. Although the cost of actual parts used in a DRO are low, the possible problems associated with microphonics and frequency centering adds considerable manufacturing costs to a DRO as specially engineered casings are required. This results in a DRO currently costing approximately $500-600. On the other hand, a well-known CRO as described herein above can cost less than $10.
Another alternative implementation for the VCO within FIG. 1 is to replace the VC-CRO 28 stabilized with a ceramic coaxial resonator with a Yttrium Iron Garnet (YIG) stabilized oscillator. These oscillators can operate at sufficiently high frequencies with low noise throughout the tuning bandwidth. Unfortunately, there are a number of unacceptable disadvantages to their use. For one, the tuning of these YIG devices is relatively slow (300 KHz modulation bandwidth versus a typical 2 MHz modulation bandwidth for a VC-CRO) due to the use of an inductor within the tuned circuit. Other disadvantages include the high current consumption of these oscillators and their relatively high cost when compared to the VC-CRO. A minimum cost for a YIG stabilized oscillator is approximately $90. Due to these problems, YIG stabilized oscillators are used seldom in industry except within measurement equipment.
The advantages of using a ceramic coaxial resonator to stabilize an oscillator within a PLL frequency synthesizer are especially apparent when compared to the alternative designs discussed above. The simple design of a ceramic coaxial resonator is not sensitive to microphonics as there are no placement or cavity requirement, unlike the dielectric resonator implementation. Further, the tuning of a VC-CRO is sufficiently fast to be used within a variety of applications, unlike the tuning of a YIG stabilized oscillator. A key advantage, as a result of the other advantages, is the high performance quality with a low cost. The disadvantage is, as discussed previously, the physical limitation to the size of a ceramic resonator that further causes a limitation to the achievable oscillation frequency.
Another significant limitation to the overall design of a CRO concerns the components used within the PLL-FS, as will be described herein below. Although the block diagrams of FIGS. 1 and 2 accurately depict typical block diagrams for PLL-FS designs, in reality, PLL-FS designs normally have the first frequency divider 22, the phase detector 24 and at least a portion of the second frequency divider 36 combined within a single component, hereinafter referred to as a PLL synthesizer chip. FIG. 3 illustrates a modified block diagram of FIG. 1 for the case that a PLL synthesizer chip 45 incorporates the first frequency divider 22, the phase detector 24 and an internal frequency divider 46. In this case, the second frequency divider 36 is the combination of the internal frequency divider 46 and an external frequency divider 47 coupled between the coupler 30 and the internal frequency divider 46. The main input/outputs for this synthesizer PLL chip 45 include a reference input from the crystal oscillator 20, a feedback input from the external frequency divider 47 and an output to the filter loop 26.
One significant problem for the overall PLL-FS design of FIG. 3 results from the frequency operating parameters with relation to the feedback input of the PLL synthesizer chip 45, this operating parameter setting a maximum frequency level for the feedback input. Currently, this maximum frequency level is limited to approximately 2.8 GHz. In the next couple of years, this value is expected to increase to such values as 4.0 or 6.0 GHz due to advancements in technology. Unfortunately, in traditional designs, this limitation restricts the output frequency of the CRO 28 unless a frequency divider, like the external frequency divider 47, is implemented between the CRO 28 and the PLL synthesizer chip 45. The difficulties with using external frequency dividers include the resulting increases in phase noise, cost and physical size for the overall PLL-FS. This increased phase noise is particularly troubling due to the external frequency divider being implemented within the feedback path, where the PLL-FS is particularly sensitive of phase noise.
Hence, an alternative implementation for a VCO is required that can satisfy high oscillation frequency requirements while maintaining the advantages gained with the use of ceramic coaxial resonators. Preferably, such a design would further compensate for the limitations within the PLL synthesizer chips so that external frequency dividers would not be necessary.